The present invention relates to a step-up converter based on an integrated transformer. More particularly, the invention relates to a step-up converter based on an integrated transformer that can be used as an alternative or a complement to conventional capacitive charge pump circuits.
In many fields of integrated electronics, as in the case of memory integration, some fundamental operations cannot be performed by applying only the low voltages of the power supply: one example is given by the write and delete operations of Flash and EEPROM memories. This aspect becomes more important in the field of microcontrollers with integrated Flash memories, where increasingly extreme scaling of the supply voltages contrasts with a substantial stability of the voltage levels required for programming. The task of capacitive charge pumps is therefore to generate voltage values higher than the power supply by using capacitors as storage systems in which the charge that will accumulate toward the output is made to pass. One of the most significant parameters for describing the performance of a charge pump is its efficiency, whose maximization has been the focus of the efforts made in recent years to improve known voltage booster architectures.
One characteristic that is common to all charge pumps is that it is impossible to achieve a complete charge transfer from one stage to the next, due to the loss of a threshold voltage of each one of the MOS used as diodes or due to the excessive channel resistance of the pass transistors. In particular, when the transistors are connected as diodes, the asymptotic charging level reached between one stage and the next is equal to the supply voltage minus a threshold VT, which becomes increasingly important as one approaches the last stages of the pump, where the body effect becomes predominant.
In the current background art, the charge pumps most frequently used to generate the high voltage levels required for the operation of non-volatile memories are based on control systems with four phases without voltage boosting. One rather valid architecture is also the one that uses a simple system with two phases, assisted by an operating frequency that is higher than the ones normally used.
The typical diagram of a four-phase NMOS charge pump is shown in FIG. 1, which shows generic stages. In addition to the gate precharge circuits, there are often branches for precharging to Vdd for the intermediate nodes of the pump.
Each stage is composed of a boost capacitor C(k) and by a pass transistor M(k); the figure also shows a switch M′(k), whose purpose is to precharge the node PRE(k) and the four phases A, B, C and D, whose timing is shown in FIG. 2. Both the boost phases B and D and the control phases A and C vary between 0 and Vdd. When B goes high, the phase D has not yet reached 0 and the transistor M′(k) remains on, allowing to precharge the mode PRE(k) up to the potential value of the node k. Then C switches, and D reaches the low logic value, switches off M′(k) and allows the isolation of the node PRE(k). The phase C provides a miniboost effect on the gate of the transistor M(k), switching it on and partly limiting the problems linked to threshold voltage loss.
The packet of charge is transferred from the capacitor C(k) to the capacitor of the next stage C(k+1). When C and D switch again, the pass transistor opens and the node PRE(k) returns to the potential of the node k by virtue of M′(k) as soon as B has returned to the low value. In order to minimize the problems introduced by the body effect on the increase in the threshold voltages, suitable circuits for biasing the NMOS that provide the pass transistors are used, utilizing a partitioned version of the output voltage of the pump.
The architecture with two phases with voltage boost of the controls and low-voltage transistors is based on the use of low-voltage transistors for the execution of the individual stages and furthermore utilizes higher operating frequencies than used in conventional solutions (100 MHz instead of 10–20 MHz). The output resistance of a capacitive charge pump can in fact be reduced by increasing the operating frequency and by using MOS transistors with a low threshold to speed up the charge transfer operations. However, this type of approach forces the use of low-voltage transistors, which due to problems linked to possible oxide punch-through cannot withstand at their terminals voltages higher than the power supply. The single stage and a general diagram of a three-stage charge pump are shown in FIGS. 3 and 4. Each stage allows to obtain, in theory, a gain equal to the supply voltage, is provided without resorting to high-voltage MOS and is driven by two phases which must be perfectly nonoverlapping.
After an initial transient, a stationary situation is established. During the first half-cycle, ck=Vdd, ck_neg=0, M0 and M6 are on, M1 and M5 are off; C1 is charged to Vlow and Vhigh is charged to the value stored in C0 (i.e., Vlow) plus Vdd. During the second half of the cycle, ck=0, ck_neg=Vdd, M0 and M6 are off, M1 and M5 are on; C0 is charged to Vlow and Vhigh is charged to Vlow+Vdd. In this manner, a gain in voltage between Vlow and Vhigh is achieved whose ideal value is Vdd and can be approximated, ignoring losses due to an insufficiently high overdrive, as:
            Δ      ⁢                          ⁢      v        =                            V          dd                ·                  C                      C            +                          C              par                                          -                        R          out                ·                  I          out                                R      out        =                  1                  f          ·          C                    +              R        switch            where C=C0=C1; Cpar indicates the parasitic capacitances of the internal nodes of the individual stage, Rout is the output resistance of the charge pump, and Rswitch is the channel resistance of each MOS.
If n stages are cascade-connected, one obtains:Vout=Vdd+n·Δv The main cause of power dissipation is constituted by the driving stages that lie downstream of the clocks. The formula used to calculate the efficiency is given hereafter:
  η  =            100      ⁢              %        ·                              P            out                                P            in                                =          100      ⁢              %        ·                                            V              out                        ·                          I              out                                                          V              dd                        ·                                          I                _                            ⁡                              (                                  V                  dd                                )                                                        
where I(Vdd) and Vout are the average values of I(Vdd) and Vout.
A series of measurements was taken on 3- and 5-stage pumps implemented in 0.18-μm technology (6 levels of metal) with NMOS in triple well and supply voltages between 1.6 and 2V as the current drawn at the output and the frequency of the two phases varied. The results have shown a bell-curve behavior of the efficiency as the output current varies, with a peak around 350 μA. Other advantages of the high frequencies used are a rather short rise time and a reduction in the ripple on the output voltage.
The drawbacks of conventional capacitive charge pump circuits are high chip area occupation, long output rise time, and the lack of the possibility to adjust the output voltage of said circuit.